CHIP DESIGN · COURSE

Analog & Mixed-Signal IC Foundations

Build analog and mixed-signal reasoning from measurable quantities rather than unexplained circuit recipes. Establish references, signs, units, KCL/KVL, loading, operating points, and small-signal boundaries; derive MOS bias, transconductance, output resistance, amplifier gain, differential behavior, poles, zeros, bandwidth, slew, feedback, stability, and compensation; integrate noise spectral density, distortion, mismatch, and process variation; connect sampling and aliasing to quantization, ADC/DAC architecture, references, and clocks; and finish with PLL concepts, executable analog–digital interface contracts, bounded behavioral models, fault mutations, and a converter-front-end capstone that states exactly which schematic, statistical, layout, package, manufacturing, and silicon claims remain open.

Before this course: Completed CMOS & VLSI Foundations. Algebra, complex-number notation, derivatives, integrals, first-order differential equations, KCL, KVL, RC circuits, MOS regions, and decibels are introduced or reviewed before advanced use. Differential Equations is recommended but not required by the chip-design dependency graph. No SPICE installation, proprietary model, analog simulator license, layout editor, PDK, foundry data, package model, RF laboratory, or fabricated silicon is assumed.

COURSE FACTSStage, chapters, units, prerequisite, and outcome
Chapter 1

Voltage, current, power, and references require signs and units

Objective: For “Voltage, current, power, and references require signs and units,” which operating condition owns the result, which equation proves it, and which single mutation should cause the first visible failure?

Voltage is a potential difference V_ab=V_a−V_b; current direction is declared; passive-sign power is p=vi. Analog design follows continuous voltages, currents, charge, time, and probability rather than ideal Boolean levels. Name the reference node, signal polarity, bias point, device region, units, source and load impedances, process-voltage-temperature corner, frequency range, and approximation before calculating. The first-order model should expose cause and direction; higher-fidelity simulation is evidence only after its models, options, initial conditions, and measured quantities are frozen.

KCL conserves charge at a node and KVL conserves potential around a lumped loop. Derive the relationship from KCL, KVL, charge conservation, a stated device equation, or a linearized transfer function; do not begin with a memorized formula detached from its sign convention. The worked trace is A 1.2 V source drives 1 kΩ and 2 kΩ in series; compute current, node voltage, and resistor powers. The boundary is Changing a voltage reference or current arrow without changing signs creates a plausible but inconsistent result. Hand calculation, operating-point audit, sweep, transient, noise, and corner/Monte Carlo evidence answer different questions, so agreement at one nominal point never closes the full specification.

KCL conserves charge at a node and KVL conserves potential around a lumped loop. This invariant is valid only inside the declared device region, small-signal or large-signal regime, linearity range, loop condition, sampling phase, and model accuracy.

For “Voltage, current, power, and references require signs and units,” begin from this exact contract: Voltage is a potential difference V_ab=V_a−V_b; current direction is declared; passive-sign power is p=vi. Draw the relevant signal and current directions, establish the operating condition, and write the governing conservation equation before simplifying the model.

Use the point-specific invariant “KCL conserves charge at a node and KVL conserves potential around a lumped loop.” Preserve units and signs while reconstructing the stated case: A 1.2 V source drives 1 kΩ and 2 kΩ in series; compute current, node voltage, and resistor powers.

Challenge the derivation with its own boundary: Changing a voltage reference or current arrow without changing signs creates a plausible but inconsistent result. Identify the first violated assumption, restore the baseline, and state which simulation or measurement would test the remaining uncertainty.

A 1.2 V source drives 1 kΩ and 2 kΩ in series; compute current, node voltage, and resistor powers. Predict sign, order of magnitude, dominant limit, and expected waveform or code before following the arithmetic.

  1. For “Voltage, current, power, and references require signs and units,” freeze the values and units in this case: A 1.2 V source drives 1 kΩ and 2 kΩ in series; compute current, node voltage, and resistor powers. Convert prefixes explicitly and identify the operating or sampled initial condition.
  2. Apply “KCL conserves charge at a node and KVL conserves potential around a lumped loop.” one step at a time and retain the intermediate quantity that decides the result instead of jumping to a memorized formula.
  3. Test the computed result against “Changing a voltage reference or current arrow without changing signs creates a plausible but inconsistent result.” Capture the first divergence, restore the original case, and state the model, layout, corner, or measurement evidence still missing.

Result: KCL conserves charge at a node and KVL conserves potential around a lumped loop. The numerical trace is accepted only for the stated model and conditions; record margin to the closest failed assumption and the next simulation or measurement needed.