CHIP DESIGN · COURSE

Cell Libraries, SRAM, I/O & IP Qualification

Qualify the dependencies that a real ASIC cannot replace with ideal RTL. Start with claim-to-evidence matrices and the different ownership boundaries of soft, firm, and hard IP. Reconcile standard-cell functions, timing arcs, Liberty tables, power/noise data, LEF abstracts, layouts, extraction, characterization, corners, and updates. Carry SRAM compiler identity through cycle-accurate semantics, sleep/retention, timing, power, MBIST, repair, ECC, and floorplanning. Connect I/O modes, voltage and load envelopes, ESD structures, pad rings, and package maps. Bound PLL, reset, regulator, sensor, trim, calibration, OTP, test, and firmware assumptions. Treat legal permission, provenance, vulnerabilities, patches, supplier support, and archival reconstruction as technical dependencies. Finish with a complete IP bill of materials, nine cross-view fault injections, independent review, and a decision that separates modeled integration evidence from real silicon qualification.

Before this course: Completed Semiconductor Fabrication, PDKs & Design Rules; Static Timing, CDC & Constraints; Physical Design, Power & Signal Integrity; Design for Test; SoC Integration; Analog & Mixed-Signal Foundations; Tapeout; and EDA Automation. Exercises use synthetic or lawfully accessible artifacts. Proprietary libraries, memory compilers, I/O/ESD and analog macros, third-party IP, legal rights, supplier qualification, foundry acceptance, and fabricated-silicon evidence are not supplied.

COURSE FACTSStage, chapters, units, prerequisite, and outcome
Chapter 1

An IP data sheet is a bounded contract, not proof by reputation

Objective: For “An IP data sheet is a bounded contract, not proof by reputation,” which frozen inputs determine the result, what is the first independently observable claim, and which mutation proves the check is alive?

The contract names function, interface, timing, clocks, resets, power states, voltage, temperature, process, reliability, test, firmware, security, physical integration, package assumptions, revisions, errata, and excluded uses. This lesson uses the route “build the smallest observable case.” Begin with a hand-checkable instance before invoking automation: name the state that enters the step, the transformation that is permitted, the observation that must change, and the evidence that would falsify the claim. Define what an IP block claims, which views implement each claim, who qualified them, and which integration conditions keep the evidence valid. Connect every abstraction back to the physical structure or executable evidence it represents, and state where that representation stops being reliable.

An IP data sheet is a bounded contract, not proof by reputation has a reviewable contract: Every accepted claim maps to inspectable evidence and a complete set of consumer views for the exact IP/PDK/tool/revision combination. Name the applicable scope, identities, units, conditions, exclusions, threshold, evidence source, owner, and change rule before using the result. Separate control-plane success from design evidence: a process can exit zero while consuming the wrong revision, skipping work, reusing stale output, suppressing a violation, or publishing an incomplete artifact. A widely used IP is accepted for a new voltage and process although its qualification report covers only the prior node. The learner must identify the first divergence and repair the dependency, not merely rerun until a dashboard becomes green.

Every accepted claim maps to inspectable evidence and a complete set of consumer views for the exact IP/PDK/tool/revision combination. This invariant is accepted only for the named candidate and declared environment; any changed input invalidates every dependent result until reconstruction proves otherwise.

Freeze the exact objects, conditions, units, and source evidence in the worked case “Build a claim matrix for a UART hard macro with function, timing, power, DFT, physical, firmware, and legal rows.” First freeze the candidate and predict the expected observation without reading a generated summary.

Apply the stated physical or engineering model, showing each transformation and preserving values that fail, are missing, or remain outside the model. Then execute the smallest transformation, retaining raw standard output, standard error, exit status, generated files, and resource use.

Compare the derived observation with “Every accepted claim maps to inspectable evidence and a complete set of consumer views for the exact IP/PDK/tool/revision combination.” and identify the first downstream decision invalidated by the failure boundary. Finally reconcile the observation with the invariant, inject the named failure, and verify that the expected consumer refuses the corrupted or stale state.

Build a claim matrix for a UART hard macro with function, timing, power, DFT, physical, firmware, and legal rows. Before revealing the trace, predict the exact command or state transition, expected exit and artifact status, first checker that should react, and minimum safe recovery.

  1. Freeze the exact objects, conditions, units, and source evidence in the worked case “Build a claim matrix for a UART hard macro with function, timing, power, DFT, physical, firmware, and legal rows.”
  2. Apply the stated physical or engineering model, showing each transformation and preserving values that fail, are missing, or remain outside the model.
  3. Compare the derived observation with “Every accepted claim maps to inspectable evidence and a complete set of consumer views for the exact IP/PDK/tool/revision combination.” and identify the first downstream decision invalidated by the failure boundary.

Result: Any row without matching revision, condition, evidence, and view remains blocked regardless of vendor reputation. Accept the result only after a clean second execution reproduces the decisive artifact and a targeted mutation fails at the predicted boundary.