CHIP DESIGN · COURSE

CMOS & VLSI Foundations

Connect digital logic to its electrical and physical realization without pretending that a hand model is fabricated silicon. Begin with MOS terminals, switch abstractions, operating regions, body and leakage boundaries; derive the complementary inverter, voltage-transfer curve, switching point, gain, logic levels, and noise margins; then construct NAND, NOR, and complex static CMOS through pull-down/pull-up duality. Build capacitance, first-order RC delay, logical effort, αCV²f switching power, short-circuit and leakage models. Continue through transmission-gate storage, setup/hold/clock-to-Q, metastability, interconnect RC and crosstalk, PVT and local variation, supply and reliability boundaries, 6T SRAM, layout, DRC, LVS, and parasitic extraction. The capstone audits one standard-cell path from Boolean contract through bilingual, independently reconstructable physical evidence.

Before this course: Completed Digital Logic & Boolean Reasoning. The course assumes binary voltage levels, Boolean algebra, combinational and sequential circuits, truth tables, clocks, state, and elementary algebra. Voltage, current, resistance, capacitance, exponentials, MOS terminology, timing thresholds, and layout concepts are introduced locally. No semiconductor-device course, SPICE installation, proprietary PDK, layout tool, foundry access, or fabricated chip is assumed at the opening; optional tool adapters must identify their models and never invent results.

COURSE FACTSStage, chapters, units, prerequisite, and outcome
Chapter 1

Four terminals define a MOS device before it becomes a switch

Objective: Why must the body terminal be named? Answer by naming the governing current or charge path, the model and corner, the observation threshold, one failure boundary, and the next evidence layer.

Gate, source, drain, and body voltages control channel formation; source and drain labels are contextual in a symmetric ideal model, while body junctions and real layout break naive symmetry. CMOS design connects device behavior, transistor networks, electrical loading, timing, energy, layout, and variation. We begin from a declared abstraction and never treat a logic symbol as proof of its transistor implementation. Inputs, outputs, supplies, body connections, switching conditions, loads, activity, process assumptions, voltage, temperature, and evidence source stay visible. This lets a beginner reason with a hand model while understanding exactly what a schematic simulation, extracted simulation, static-timing report, or measured chip would add.

The local contract is “An NMOS hand model turns on when VGS exceeds a declared threshold and passes a strong low but degraded high; a PMOS turns on when VSG exceeds its magnitude threshold and passes a strong high.” Its invariant is “A valid switch-level conclusion identifies all four terminals, supply reference, body connection, controlling voltage, and intended strong logic level.” Derive the result from charge paths and state ownership before quoting a rule of thumb. Name the observation node, transition direction, initial condition, input slew, effective resistance, capacitance, and corner whenever they matter. The boundary “Calling a transistor “on” from gate voltage alone ignores source and body potential and can predict an impossible full-rail output.” is kept beside the successful case because a nominal calculation does not establish all input vectors, all transitions, every layout, or fabricated-silicon behavior.

A valid switch-level conclusion identifies all four terminals, supply reference, body connection, controlling voltage, and intended strong logic level. This invariant holds only under its declared topology, device model, stimulus, load, supply, temperature, and evidence layer; it is not automatically a statement about another cell, corner, layout, process, package, or manufactured die.

Reference every terminal voltage to the same ground and identify the lower-potential NMOS source or higher-potential PMOS source for the case. At derivation step 1, mark conducting and cut-off devices, the current or charge path, the node being changed, the approximation used, its units, and a direct check against the original specification.

Compare VGS or VSG with the declared threshold to classify the switch. At derivation step 2, mark conducting and cut-off devices, the current or charge path, the node being changed, the approximation used, its units, and a direct check against the original specification.

Trace whether the conducting path charges or discharges the output and stop when overdrive disappears or a rail is reached. At derivation step 3, mark conducting and cut-off devices, the current or charge path, the node being changed, the approximation used, its units, and a direct check against the original specification.

Use one NMOS pass device with gate at VDD to transfer a rising input toward an empty capacitor. Predict polarity, final logic level, charge path, relative delay or energy, and the evidence layer before revealing the worked trace.

  1. Initially VGS≈VDD, so the channel conducts and charges the capacitor. At trace step 1, write the input/state, active network, affected node, symbolic relation with units, and one sanity or boundary check.
  2. As output rises, VGS falls because the output-side source potential rises. At trace step 2, write the input/state, active network, affected node, symbolic relation with units, and one sanity or boundary check.
  3. Charging weakens near VOUT≈VDD−VT in the simple model, so this is not a restored strong high. At trace step 3, write the input/state, active network, affected node, symbolic relation with units, and one sanity or boundary check.

Result: The switch model predicts a threshold-degraded high, not an exact voltage for a real device. Accept this result only for the stated abstraction and conditions. A stronger claim requires the corresponding transistor models, parasitics, corner set, tool reports, calibration, or physical measurements.