CHIP DESIGN · COURSE

FPGA Engineering

Move verified RTL toward one safely configured and measured programmable device without collapsing the evidence layers. The course begins with FPGA resources, volatile configuration, exact target identity, clean projects, and executable constraints; then develops primary and generated clocks, clock enables, reset release, pin and voltage contracts, asynchronous mechanical inputs, safe outputs, block-memory and DSP inference, fixed-point arithmetic, UART/SPI-style links, versioned command buffering, synthesis reconciliation, static timing, timing closure, asynchronous FIFOs, on-chip debug, and controlled board experiments. The capstone delivers a versioned command-and-telemetry system with a portable core, narrow board adapter, clean rebuild, five fault classes, and an honest zero-board path.

Before this course: Completed RTL Design with SystemVerilog and Functional Verification. The course assumes synthesizable RTL, valid-ready protocols, assertions, scoreboards, timing and CDC vocabulary, but no vendor FPGA tool installation or board is required until an explicitly named adapter experiment; no private license or specific vendor flow is hidden in the opening.

COURSE FACTSStage, chapters, units, prerequisite, and outcome
Chapter 1

Programmable fabric maps logic into heterogeneous resources

Objective: Why not promise one BRAM? Answer by naming the evidence layer, exact device or model, responsible constraint/resource, failure boundary, and one claim still unproved.

An FPGA combines lookup tables, flip-flops, carry chains, block memories, DSP slices, clock networks, I/O cells, routing, and configuration memory rather than behaving as an unlimited grid of gates. FPGA engineering connects a cycle-accurate RTL contract to one configured programmable device, but every step adds a new evidence boundary. Simulation interprets source semantics; synthesis infers a device-specific netlist; implementation places and routes resources under constraints; bitstream generation packages configuration; and a board experiment observes one physical assembly, clock, voltage, temperature, cable, and instrument setup. A successful result at one layer never silently proves the next.

The engineering contract is: For every RTL block, declare expected resource class and acceptable alternatives: combinational logic→LUT/carry, state→flip-flop, array→distributed/block memory, arithmetic→LUT/carry or DSP. The invariant is: Every inferred state element and major arithmetic/memory object in the synthesis report traces to written RTL intent. Before invoking a vendor flow, record board and exact part, top module, source and constraint revisions, tool/version, IP identities, clock/reset assumptions, I/O voltage and bank ownership, parameter values, expected resources, timing requirements, programming method, and rollback or power-down procedure. The failure “A reset on every array bit can prevent block-RAM inference and create thousands of flip-flops without changing RTL simulation.” remains a deliberate diagnostic target rather than something hidden by a green summary.

Every inferred state element and major arithmetic/memory object in the synthesis report traces to written RTL intent. The invariant applies only to the named source, constraints, device, and evidence layer; it does not by itself establish another board revision, speed grade, voltage, temperature, tool release, production unit, or fabricated ASIC.

Elaboration resolves parameters and generated hierarchy. At engineering step 1, map the requirement to the exact RTL owner, constraint or physical resource, report object, and observable check before accepting the transition.

Synthesis recognizes Boolean, sequential, memory, and arithmetic patterns. At engineering step 2, map the requirement to the exact RTL owner, constraint or physical resource, report object, and observable check before accepting the transition.

Technology mapping chooses legal resources for the exact target part under optimization settings. At engineering step 3, map the requirement to the exact RTL owner, constraint or physical resource, report object, and observable check before accepting the transition.

Predict resources for a 256×16 synchronous single-port memory with registered output. Predict the report, timing trace, or board observation before revealing it, and label which facts come from a model, tool report, logic analyzer, oscilloscope, or host transcript.

  1. Capacity is 4096 bits and access is synchronous. At trace step 1, record clock/reset epoch, transaction or sample identity, raw bits, interpreted value, constraint/resource owner, expected observation, actual observation, and status.
  2. Pattern is compatible with a small block RAM or distributed memory depending on target and directives. At trace step 2, record clock/reset epoch, transaction or sample identity, raw bits, interpreted value, constraint/resource owner, expected observation, actual observation, and status.
  3. Inspect inferred memory type, depth/width, output register, and fallback mapping in the report. At trace step 3, record clock/reset epoch, transaction or sample identity, raw bits, interpreted value, constraint/resource owner, expected observation, actual observation, and status.

Result: The prediction names acceptable resource classes; only the target synthesis report establishes the chosen mapping. Accept the result only after a clean rebuild reproduces the artifact, the relevant report and observation agree with the written contract, and one targeted change or boundary case fails at the expected checker.