CHIP DESIGN · COURSE

Physical Design, Power & Signal Integrity

Turn a logically verified gate-level block into a reproducible physical implementation. Begin with a frozen netlist, constraints, libraries, technology views, RC corners, power intent, and MMMC matrix; then reason through floorplanning, macro and pin placement, power-grid construction, placement and routability, clock-tree synthesis, detailed routing, parasitic extraction, crosstalk, setup and hold closure, engineering change orders, activity-based power, static and dynamic IR drop, electromigration, thermal feedback, DRC, LVS, ERC, density, DFM, and release reconciliation. Every chapter links a hand calculation to a full report, a controlled mutation, collateral checks, and an explicit boundary between modeled implementation evidence and fabricated-silicon claims.

Before this course: Completed CMOS & VLSI Foundations and Static Timing, CDC & Constraints. The course assumes transistor-to-gate delay and energy intuition, standard-cell and interconnect basics, setup and hold equations, generated clocks, exceptions, variation, CDC/RDC protocols, and gate-level netlist reading. No commercial place-and-route license, foundry rule deck, proprietary library, production design, tapeout authority, or silicon laboratory is assumed; examples use hand-checkable models and tool-neutral evidence contracts.

COURSE FACTSStage, chapters, units, prerequisite, and outcome
Chapter 1

A reproducible handoff freezes logical and physical intent

Objective: What exact input identity, physical rule, metric, collateral check, and evidence boundary make “A reproducible handoff freezes logical and physical intent” reproducible?

Implementation begins only when the synthesized netlist, SDC, timing/power libraries, abstract physical views, technology rules, RC models, UPF or power intent, and MMMC scenario set have compatible identities. Physical design turns a logically verified gate-level design into placed cells, clock networks, routed conductors, extracted parasitics, and release data. Every action therefore has four named layers: the design object being changed, the constraint or physical rule that makes the change legal, the metric expected to improve, and the collateral metrics that must be rechecked. Before reading a colored heat map or a summary number, identify the netlist, constraint mode, PVT and RC corner, physical database, activity source, tool version, command, units, and report scope.

The local engineering contract is “The handoff manifest hashes every input, names tool/version and units, maps logical cells to physical views, and rejects missing clocks, unresolved references, inconsistent sites, or unowned warnings.” Its invariant is “Reopening the same manifest produces the same design objects, clocks, library mappings, units, and declared scenarios before optimization.” Work from a small hand-checkable model before trusting automation: name boundaries, trace one representative path or current route, predict direction and order of magnitude, run the transformation, and reconcile the result with an independent report. The failure boundary “A clean synthesis log cannot compensate for a missing generated clock, mismatched LEF width, wrong RC corner, or stale power intent.” remains explicit because timing, power, routing, electrical, reliability, manufacturability, and logical equivalence are related but distinct evidence layers.

Reopening the same manifest produces the same design objects, clocks, library mappings, units, and declared scenarios before optimization. This statement is limited to the named netlist, layout state, constraints, libraries, extracted parasitics, switching assumptions, modes, corners, and analysis settings. It is not automatically a claim about fabricated silicon frequency, power, lifetime, yield, field reliability, or every workload.

Inventory netlist modules, ports, sequential cells, clocks, tie cells, and black boxes. At derivation step 1, record the input identity, equation or rule, units, expected direction, changed object, and an independent observation that could falsify the prediction.

Cross-check Liberty cell names against LEF abstracts and technology sites/layers. At derivation step 2, record the input identity, equation or rule, units, expected direction, changed object, and an independent observation that could falsify the prediction.

Run zero-optimization timing, connectivity, power-intent, and missing-view audits and sign the manifest. At derivation step 3, record the input identity, equation or rule, units, expected direction, changed object, and an independent observation that could falsify the prediction.

A netlist uses cell NAND2_X1, but the loaded LEF has only NAND2_X2. Is the handoff complete? Before revealing the trace, predict the limiting resource, the sign and approximate magnitude of the result, one likely collateral effect, and the report that must confirm it.

  1. Logical reference NAND2_X1 is present in the netlist. At trace step 1, retain object names, units, intermediate arithmetic, tool state, pass/fail threshold, and the next evidence layer.
  2. No physical abstract can size or place that reference. At trace step 2, retain object names, units, intermediate arithmetic, tool state, pass/fail threshold, and the next evidence layer.
  3. Stop and load the matching view or regenerate a version-aligned netlist; do not silently substitute. At trace step 3, retain object names, units, intermediate arithmetic, tool state, pass/fail threshold, and the next evidence layer.

Result: The handoff fails because logical-to-physical mapping is incomplete. Accept this result only after a clean incremental rerun, the relevant coverage and violation reports, logical-equivalence or functionality evidence when the netlist changed, and one targeted mutation that fails at the predicted checker.