CHIP DESIGN · COURSE

Product Engineering, ATE, Yield & Reliability

Turn manufactured die into controlled production decisions. Map product and defect risks across wafer sort, package test, system test, characterization, stress, outgoing audit, and field monitoring. Build tester-resource and load-board contracts with calibrated conditions, compliance, contact health, site diagnostics, and bench/tester correlation. Convert DFT, patterns, timing, levels, firmware, trims, and parametric algorithms into immutable test-program releases. Characterize real populations across lots, wafers, die positions, packages, voltage, temperature, modes, equipment, and time; derive limits and guardbands without post-hoc changes or double counting. Preserve unique-unit denominators through retest, repair, bins, Pareto, wafer maps, diagnosis, and yield learning. Quantify escapes, overkill, sampling uncertainty, zero-failure upper bounds, and production drift. Connect mission profiles to mechanism-specific reliability stress and censored populations. Control excursions, containment, corrective action, changes, and cost. Finish with independent raw-data reconstruction and an authorized 20-row production release or hold.

Before this course: Completed DFT & Manufacturing Test; Tapeout, Yield & Silicon Bring-up; EDA Automation; PDK/Design Rules; IP Qualification; Embedded Firmware; and Package/PCB/Lab Engineering. Requires probability, statistics, regression, confidence intervals, measurement uncertainty, scripting/data analysis, and safe lab practice. Real completion requires traceable silicon populations, ATE/prober/handler, load boards/probe cards/sockets, calibrated labs, environmental/reliability equipment, foundry/assembly/test partners, quality systems, destructive analysis, inventory authority, and independent release ownership.

COURSE FACTSStage, chapters, units, prerequisite, and outcome
Chapter 1

A test strategy maps risks and claims to stages and observability

Objective: For “A test strategy maps risks and claims to stages and observability,” which frozen inputs determine the result, what is the first independently observable claim, and which mutation proves the check is alive?

Wafer sort, package test, burn-in or stress, board/system test, calibration, outgoing audit, and field monitoring differ in access, cost, temperature, parallelism, repair, and detectable mechanisms. This lesson uses the route “build the smallest observable case.” Begin with a hand-checkable instance before invoking automation: name the state that enters the step, the transformation that is permitted, the observation that must change, and the evidence that would falsify the claim. Translate datasheet, manufacturing, quality, reliability, cost, traceability, and shipment claims into wafer-sort, final-test, system, and audit evidence. Connect every abstraction back to the physical structure or executable evidence it represents, and state where that representation stops being reliable.

A test strategy maps risks and claims to stages and observability has a reviewable contract: Every mandatory product and manufacturing risk has a justified detection or characterization stage, stimulus, observable, limit, disposition, residual escape path, owner, and cost/time budget. Name the applicable scope, identities, units, conditions, exclusions, threshold, evidence source, owner, and change rule before using the result. Separate control-plane success from design evidence: a process can exit zero while consuming the wrong revision, skipping work, reusing stale output, suppressing a violation, or publishing an incomplete artifact. A package-open defect can arise after wafer sort, but its only test is at wafer probe and no final continuity check exists. The learner must identify the first divergence and repair the dependency, not merely rerun until a dashboard becomes green.

Every mandatory product and manufacturing risk has a justified detection or characterization stage, stimulus, observable, limit, disposition, residual escape path, owner, and cost/time budget. This invariant is accepted only for the named candidate and declared environment; any changed input invalidates every dependent result until reconstruction proves otherwise.

Freeze the exact objects, conditions, units, and source evidence in the worked case “Map ten defect/risk classes to wafer, package, system, audit, and field stages with cost and observability.” First freeze the candidate and predict the expected observation without reading a generated summary.

Apply the stated physical or engineering model, showing each transformation and preserving values that fail, are missing, or remain outside the model. Then execute the smallest transformation, retaining raw standard output, standard error, exit status, generated files, and resource use.

Compare the derived observation with “Every mandatory product and manufacturing risk has a justified detection or characterization stage, stimulus, observable, limit, disposition, residual escape path, owner, and cost/time budget.” and identify the first downstream decision invalidated by the failure boundary. Finally reconcile the observation with the invariant, inject the named failure, and verify that the expected consumer refuses the corrupted or stale state.

Map ten defect/risk classes to wafer, package, system, audit, and field stages with cost and observability. Before revealing the trace, predict the exact command or state transition, expected exit and artifact status, first checker that should react, and minimum safe recovery.

  1. Freeze the exact objects, conditions, units, and source evidence in the worked case “Map ten defect/risk classes to wafer, package, system, audit, and field stages with cost and observability.”
  2. Apply the stated physical or engineering model, showing each transformation and preserving values that fail, are missing, or remain outside the model.
  3. Compare the derived observation with “Every mandatory product and manufacturing risk has a justified detection or characterization stage, stimulus, observable, limit, disposition, residual escape path, owner, and cost/time budget.” and identify the first downstream decision invalidated by the failure boundary.

Result: Post-assembly risks retain a downstream detector; early passing evidence cannot cover later-added defects. Accept the result only after a clean second execution reproduces the decisive artifact and a targeted mutation fails at the predicted boundary.