CHIP DESIGN · COURSE

Semiconductor Fabrication, PDKs & Design Rules

Connect drawn layout to the physical process that must manufacture it. Build cross-sections through lithography, etch, deposition, implantation, anneal, and CMP. Identify qualified MOS, well, isolation, latch-up, pad, ESD, high-voltage, metal, and via structures, then reason about their three-dimensional parasitic and reliability context. Audit the coordinated files and compatibility rules inside a PDK, derive geometric and conditional design rules from physical risks, and reconstruct layout through DRC, LVS, ERC, antenna, extraction, and stream readback. Distinguish deterministic corners from statistical variation and lifetime projections. Treat fill, lithography hotspots, DFM, and foundry notices as evidence-changing transformations. Finish by auditing one real or synthetic PDK release with positive and negative regression cells and a bounded use decision.

Before this course: Completed CMOS & VLSI Foundations; Static Timing, CDC & Constraints; Physical Design, Power & Signal Integrity; Tapeout, Yield & Silicon Bring-up; and EDA Automation & Reproducible ASIC Flows. Calculus, elementary probability, circuits, semiconductor-device basics, coordinate geometry, and Linux scripting are required. Proprietary PDKs, foundry decks, device models, tool licenses, process correlation, and fabrication authority require lawful external access and are not supplied by this course.

COURSE FACTSStage, chapters, units, prerequisite, and outcome
Chapter 1

A process flow is an ordered transformation of material and topology

Objective: For “A process flow is an ordered transformation of material and topology,” which frozen inputs determine the result, what is the first independently observable claim, and which mutation proves the check is alive?

Each fabrication step changes composition, thickness, stress, geometry, or dopant distribution; later masks operate on the state left by all earlier steps. This lesson uses the route “build the smallest observable case.” Begin with a hand-checkable instance before invoking automation: name the state that enters the step, the transformation that is permitted, the observation that must change, and the evidence that would falsify the claim. Connect oxidation, deposition, lithography, etch, implantation, diffusion, anneal, and planarization to the shapes and electrical properties visible to design. Connect every abstraction back to the physical structure or executable evidence it represents, and state where that representation stops being reliable.

A process flow is an ordered transformation of material and topology has a reviewable contract: A legal device cross-section must be reachable by the exact ordered process modules declared by the foundry, not merely drawable as overlapping polygons. Name the applicable scope, identities, units, conditions, exclusions, threshold, evidence source, owner, and change rule before using the result. Separate control-plane success from design evidence: a process can exit zero while consuming the wrong revision, skipping work, reusing stale output, suppressing a violation, or publishing an incomplete artifact. Swapping implant and gate-pattern order changes self-alignment and junction placement even when final layer names look similar. The learner must identify the first divergence and repair the dependency, not merely rerun until a dashboard becomes green.

A legal device cross-section must be reachable by the exact ordered process modules declared by the foundry, not merely drawable as overlapping polygons. This invariant is accepted only for the named candidate and declared environment; any changed input invalidates every dependent result until reconstruction proves otherwise.

Freeze the exact objects, conditions, units, and source evidence in the worked case “Trace a simplified well, isolation, gate, source/drain, contact, and metal sequence through six cross-sections.” First freeze the candidate and predict the expected observation without reading a generated summary.

Apply the stated physical or engineering model, showing each transformation and preserving values that fail, are missing, or remain outside the model. Then execute the smallest transformation, retaining raw standard output, standard error, exit status, generated files, and resource use.

Compare the derived observation with “A legal device cross-section must be reachable by the exact ordered process modules declared by the foundry, not merely drawable as overlapping polygons.” and identify the first downstream decision invalidated by the failure boundary. Finally reconcile the observation with the invariant, inject the named failure, and verify that the expected consumer refuses the corrupted or stale state.

Trace a simplified well, isolation, gate, source/drain, contact, and metal sequence through six cross-sections. Before revealing the trace, predict the exact command or state transition, expected exit and artifact status, first checker that should react, and minimum safe recovery.

  1. Freeze the exact objects, conditions, units, and source evidence in the worked case “Trace a simplified well, isolation, gate, source/drain, contact, and metal sequence through six cross-sections.”
  2. Apply the stated physical or engineering model, showing each transformation and preserving values that fail, are missing, or remain outside the model.
  3. Compare the derived observation with “A legal device cross-section must be reachable by the exact ordered process modules declared by the foundry, not merely drawable as overlapping polygons.” and identify the first downstream decision invalidated by the failure boundary.

Result: The cross-section is accepted only when every material boundary and doped region has a producing step and compatible predecessor state. Accept the result only after a clean second execution reproduces the decisive artifact and a targeted mutation fails at the predicted boundary.