CHIP DESIGN · COURSE

Static Timing, CDC & Constraints

Build timing and clock-domain-crossing closure from explicit event relationships rather than green summaries. The course derives clocks, timing paths, setup, hold, clock-to-Q, combinational delay, skew, uncertainty, generated clocks, I/O budgets, multicycle and false-path exceptions, PVT/RC corners, variation, pulse checks, synchronizers, event transfers, handshakes, Gray-coded asynchronous FIFOs, reset-domain crossings, constraint coverage, waivers, and a reproducible signoff packet. Every worked trace retains edges, identities, units, signs, assumptions, and the first failure checker.

Before this course: Completed RTL Design with SystemVerilog and CMOS & VLSI Foundations. The course assumes synchronous state, valid-ready protocols, basic metastability vocabulary, clock-to-Q, setup/hold, RC delay, and PVT concepts. No STA/CDC tool, proprietary timing library, extracted netlist, foundry PDK, or fabricated chip is required at the opening; optional adapters must identify exact inputs and report only executed evidence.

COURSE FACTSStage, chapters, units, prerequisite, and outcome
Chapter 1

A clock is a waveform and event sequence, not only a frequency

Objective: Why retain falling edges for positive-edge registers? Answer by naming clocks, endpoints, edge pair or protocol, assumptions, evidence, and one conclusion still unproved.

A timing clock declares period, active and inactive edges, duty cycle, source pin or port, phase, latency treatment, and relationship to other clocks. Static timing and clock-domain crossing analysis answer different but connected questions. Timing analysis proves bounded path relationships under declared clocks, delays, corners, variation, and exceptions without enumerating input vectors. CDC analysis proves that asynchronous phase relationships are handled by a protocol and suitable physical structure. Every conclusion names launch and capture events, data identity, clock relationship, path endpoints, minimum or maximum delay sense, and the exact evidence layer.

The local timing or CDC contract is “Clock clk has rising edges at 0,10,20 ns, falling edges at 4,14,24 ns, period 10 ns, and a 40% high pulse.” Its invariant is “Every sequential timing check references a named launch and capture edge from declared clock waveforms.” Draw the clock and data timeline before using a report number. Separate source latency, network latency, skew, uncertainty, clock-to-Q, combinational delay, setup, hold, recovery, removal, and pulse width. The failure “Defining only 100 MHz while assuming a 50% duty cycle can miss falling-edge paths and minimum high/low pulse violations.” stays visible because a green setup summary cannot close hold, CDC, reset, unconstrained paths, false exceptions, or another PVT corner.

Every sequential timing check references a named launch and capture edge from declared clock waveforms. The invariant applies only to the named netlist, constraints, libraries, parasitics, modes, corners, clock relationships, and CDC/RDC assumptions; it is not automatically a silicon-frequency, yield, lifetime, or unrelated-mode guarantee.

Convert frequency or specification into a period with units. At derivation step 1, place the exact clock edge, data launch or protocol event, early/late path contribution, required observation, units, and sign convention before computing slack or accepting the crossing.

Place rising and falling edges from waveform and phase. At derivation step 2, place the exact clock edge, data launch or protocol event, early/late path contribution, required observation, units, and sign convention before computing slack or accepting the crossing.

Bind registers, ports, generated clocks, and pulse checks to those events. At derivation step 3, place the exact clock edge, data launch or protocol event, early/late path contribution, required observation, units, and sign convention before computing slack or accepting the crossing.

List the first four edges of a 10 ns clock whose first rise is 2 ns and high time is 3 ns. Predict the edge relationship, path type, expected slack or protocol observation, and failure checker before revealing the trace.

  1. First rising edge is 2 ns. At trace step 1, record edge time, data or token identity, clock/path contribution, accumulated arrival or requirement, and current status.
  2. First falling edge is 2+3=5 ns. At trace step 2, record edge time, data or token identity, clock/path contribution, accumulated arrival or requirement, and current status.
  3. Next period adds 10 ns, giving rise 12 ns and fall 15 ns. At trace step 3, record edge time, data or token identity, clock/path contribution, accumulated arrival or requirement, and current status.

Result: The edges are rise 2, fall 5, rise 12, fall 15 ns. Accept the result only after coverage reports show the intended path or crossing is analyzed and one targeted mutation fails at the expected checker.