Function before syntax
Boolean behavior, state, and timing are defined before an HDL describes them.
Follow the signal from a Boolean requirement to working silicon.
Chip design is a chain of specifications and physical constraints. The curriculum keeps function, time, electrical behavior, verification evidence, manufacturing test, and silicon observations connected.
Digital Logic & Boolean Reasoning is complete and open. The remaining eleven courses stay closed until both languages, labs, and usability checks are complete.
01 / CURRICULUM
Twelve courses from logic to first silicon.
A planned card is not a published course. Availability appears only when the specification, explanations, timing traces, failure cases, labs, and bilingual review are complete.
02 / WHY THIS ORDER
Each layer supplies evidence required by the next.
The route is organized by engineering dependency, not by tool popularity.
Specification before verification
A test can only provide evidence after expected behavior and forbidden behavior are explicit.
Logical and physical truth stay connected
A correct truth table does not prove timing, power, noise, manufacturability, or reliability.
Reports are claims, not decoration
Synthesis, coverage, timing, power, DRC, test, yield, and lab data must trace back to one versioned design and constraint set.
Specify, derive, trace, break, verify, and build.
- State the interface, clock, reset, state, legal inputs, outputs, latency, and failure behavior.
- Derive the circuit or protocol before writing tool-specific syntax.
- Trace ordinary, boundary, simultaneous, reset, and fault cases cycle by cycle.
- Use executable checks and a lab artifact to distinguish confidence from evidence.